1. Field of the Invention
The present invention relates to synchronization of data, and more particularly, to a low latency method of synchronizing high-speed data to a local clock domain, where the high-speed data passes from one clock domain, across an asynchronous boundary, and into the local clock domain, enabling receipt and transfer of the high-speed data within an integrated circuit according to a local clock.
2. Background Art
Newer communications systems require advanced processing of high speed digital signals in order to accommodate precise timing requirements. For example, processor-based communications systems utilize high speed bus architectures, such as HyperTransport™ bus architectures, to transfer large groups of data at high data rates. For example, the HyperTransport™ Specification specifies data transfer between discrete components (e.g., between a microprocessor and a PCI bridge) in data groups (packets) of up to 64 bytes, at prescribed data rates of 400 Megabits per second (Mbs) up to 2.0 Gigabits per second (Gbs) per wire.
Such high speed bus architectures are based on a sending device and a receiving device each using a corresponding local clock to provides a corresponding timing reference for internal data processing logic. Accordingly, communications internal to each device are based on the corresponding local clock. Hence, each device in a computing system may be configured to generate and transmit communications to other devices in the computing system based on the corresponding local clock of the transmitting device.
Devices in the computing system may be configured to operate in either a synchronous data communication mode or an asynchronous data communication mode. In the synchronous mode, the local clocks of the respective transmitting and receiving devices are derived from a common time base. Thus, the transmission and receipt of data is synchronous to the common time base, although the core clocks in the transmitting and receiving devices may have different frequencies. Note, however, that despite the common time base, the synchronization of data at the high data rates of 400 Mbs to 2.0 Gbs per wire is not trivial due to skew and phase locked loop (PLL) issues. In synchronous mode, the receiver can rely on the fact that the frequencies of the associated clocks will, when averaged over a long period of time, result in a fixed, simple ratio.
In the asynchronous mode, the local clock in the transmitting device (i.e., the transmitting clock domain) is not derived from the same time base source as the local clock in the receiving device (i.e., the receiving clock domain). Hence, the data may not be received and sampled accurately in the receiving device because the receiver cannot simply rely on a fixed, simple ratio of clock frequencies as described above.
Hence, the problem being addressed, in both synchronous and asynchronous mode, can be described as follows. Data is transmitted in one clock domain, and latched in a receiver based on a clock driven from the transmitter. The goal is to read at the data in the receiver, with the lowest possible latency. However, if the data is read too closely to the point where the data was latched, the data will be inaccurate (“bad data”) due to metastability effects. Hence, there is a need to be able to drive the synchronized data out into the receiver clock domain at the earliest possible safe time.
U.S. Patent Application Publication No. US 2002/0087909 by Hummel et al. describes a low latency synchronization of asynchronous data, where the frequency of the transmit clock domain is calculated based on the receipt of transmit data at a determined data rate. In particular, Hummel et al. utilizes a clock and data recovery unit configured for generating a synchronization (sync) signal: the synchronization signal is generated based on detecting an asynchronously-transmitted synchronization pattern that has a prescribed start sequence, as well as a prescribed termination (end) sequence; the synchronization signal is then supplied to a synchronizer and load pointer logic that controls a memory location pointer for a receive FIFO buffer. The synchronizer is configured to initialize and synchronize an unload pointer (used for reading a data from a specified location in the receive FIFO buffer) in a manner that minimizes errors due to instability. The unload pointer is initially offset by initial offset logic configured for estimating latency based on the synchronization signal, causing the unload pointer to be moved toward the load pointer to compensate for the estimated latency introduced by the synchronizer.
However, the estimated latency calculated by the device of Hummel et al. assumes an arbitrary frequency for the transmit clock domain; hence, the synchronization signal has limited precision in estimating the latency of the synchronizer. Consequently, substantial logic is need to identify the arbitrary frequency, and calculate the minimum safe time to unload the data.
In addition, the U.S. Patent Publication by Hummel et al. does not contemplate problems encountered by integrated circuit testers (i.e., chip testers) in providing a deterministic test of a receiver device. In particular, chip tester requirements often specify that the behavior of an integrated circuit tested under the conditions imposed by the chip tester must be fall within precise test parameters. However, the circuit may be capable of exhibiting multiple possible behaviors under these varying test conditions, each of which is a correct behavior. The tester, however, is only capable of checking for one specific pattern, and will consider all other behaviors failures, even if functionally the behavior is valid.
Hence, there is a concern that an integrated circuit may encounter “false failures” due to limited accepted patterns in chip test conditions.